Design Verification Engineer

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Description

APPLE INC has the following available in Austin, Texas. Perform Unit Level Verification effort for logic blocks in GPU designs. Develop Unit Level Verification test plans. Develop testbench components in UVM, e.g. checkers, monitors, etc. Develop unit-level test sequences and manage regressions. Develop scripts to be used for unit-level verification efforts. Debug simulation and silicon GPU fails. Work with cross functional teams to coordinate unit level verification. Run HDL simulation and debug failures using waveforms. Create UVM-based sequences for graphic power management testing. Create UVMbased coverage for graphics power management testing. Create Python scripts to help with flow automation. 40 hours/week.

• Master's degree or foreign equivalent in Electrical Engineering or related field.
• Experience and/or education must include:
• Creating a moderate-sized digital, analog/RF, or mixed-signal chip using industrial CAD tools and flows.
• Utilizing Python to implement data analyses.
• Planning and specification, writing a Verilog model, and designing custom circuits or synthesized standard cell blocks.
• Creating a testing/debug strategy, and full-chip integration and verification for tapeout.
• Designing and implementing testing infrastructure for chip, and writing test vectors.
• Test vector creation and test coverage evaluation.
• Architecture/microarchitecture simulators, RTL synthesis tools, and area/power/thermal modeling.

• N/A