Design Verification Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Construct a detailed test plan for various components of the design including use cases. Build coverage driven verification plans from specifications, reviewing with multi-functional teams, and refining to achieve coverage targets. Architect UVM-based, reusable test benches with components for stimulus, checkers, and reference models. Work closely with DV methodology architects to improve verification flow. Execute test plan from RTL simulation bring-up to sign-off, reporting and debugging failures, maintaining regressions, reporting verification progress against test plan and coverage metrics. Ensure a bug-free first silicon for part of the cellular modem SoC / IP. Develop detailed test plans for the design block on the micro-architecture specification. Execute verification plans, build the testbench architecture, write testcases, regression enabling, debug of the test failures, track, and report DV progress. Write functional coverage bins and analyzing both code coverage and functional cover bins and report the verification end phase trends. Understand the HW, FW and SW interaction, including usage of 3GPP stack, Layer 2 protocol, Python, and C/C++ to help in full end to end verification of modem flows. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

• Master's degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
• Education and/or experience must include each of the following skills:
• Professional design tools (architecture/microarchitecture simulators, RTL synthesis tools, and area/power/thermal modeling)
• Planning and specification, writing a Verilog model, designing custom circuits, creating a testing/debug strategy, and full-chip integration and verification
• Compilers, networks, operating systems, and computer architecture
• Design and implementation of digital circuits in a modern VLSI process technology
• Using modern computer aided design (CAD) software to design, simulate, and lay out digital circuits
• ASIC DV knowledge in reusable verification methodologies such as UVM or OVM.
• Using System C, C/C++, and Python/Perl language for automating common verification flows

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