CPU Implementation Engineer

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Description

APPLE INC has the following available in Austin, Texas. Develop and maintain STA methodologies to run static timing analysis for CPU designs and analyze its results, and ensure perfromance of the CPU with improved yield on manifacturing. Analyze top timing paths to determine the timing 'health' of the design and working with the CPU microarchitecture team to understand the key critical paths of the design inherent within the microarchitecture and facilitate logic changes to improve timing. Work with the CPU implementation team on physical timing issues, clock design, timing constraints, timing waivers, tolerance thresholds, and other physical timing issues and concerns to address any design bottlenecks and overall achieve closure. Work with the physical CAD team to enhance and improve the timing flows and infrastructure to have more diagnostic features and pre-emptive identification of silicon issues. Utilize logic design principles with timing and power implications to achieve efficient processor design and still achieving peak performance. Conduct circuit modeling, including SPICE models and worst-case corner selection to ensure operation of the CPU across worst corner conditions. 40 hours/week.

• Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related
• Education and/or experience must include each of the following:
• Scripting to parse large reporting and collect design data for statistical analysis.
• VLSI Design principles (floor planning, placement and clock tree synthesis) to handle physical design aspects of CPU core.
• Logic Design principles for understanding and ensuring efficient transferring of RTL to gate logic.
• Understanding of Timing static analysis tool and timing engine concepts (delay calc /crosstalk)
• Constraining the design in timing analysis engine, understanding of functional logic to add exceptions, and working with the design verification team.
• Programming skills to develop and enhance timing analysis flow.
• Knowledge of device physics and understanding timing and noise impacts from logic cell architectures on latest technology nodes.
• Understanding of CPU design architecture and its impact on timing, providing feedback to RTL designers to help converge design closure.
• Spice modeling and simulation to analyze standard cell performance.

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