Cellular PPAC (Power, Performance Area and Cost) Engineer

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something. Do you excel at crafting elegant solutions to complex challenges? Do you naturally prioritize the significance of every detail? As a member of our Hardware Technologies group, you'll contribute to designing, optimizing, and manufacturing our next-generation, high-performance, power-efficient cellular chips and system-on-chips (SoC). Your role will be pivotal in ensuring that Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. By joining this group, you'll be responsible for developing and building the technology that powers Apple's devices. We invite you to join us in delivering the next groundbreaking Apple products! In this highly visible position as a key technical member of the Cellular Power Performance Area & Cost optimization team, you'll play a crucial role in improving the Power, Performance, Area, and Cost efficiency metrics of Apple Cellular silicon. Your responsibilities will include optimizing Design and Implementation methodologies for cellular chips to achieve best-in-class efficiency metrics across all PPA dimensions. You'll identify and drive improvement opportunities through custom/semi-custom flows, IP development, design technology co-optimization, and advanced analytics. With practical design knowledge, you'll help differentiate and streamline Apple's silicon engineering methods.

Description

• Minimum BS and 10+ years of relevant industry experience.
• VLSI background with hands-on experience in RTL to GDSII flows.
• Prior experience in doing Power, Performance, Area and Cost optimizations for SoCs.
• Experience with SoC power flows & Vmin optimization.
• Experience with Design Technology Co-optimization, identifying and solving scaling bottlenecks in new technology nodes.
• Rapid prototyping and scripting of methodologies and test chip block implementation.

• Solid understanding of Physical Design challenges, proficiency with synthesis, place and route tools, and implementation exploration.
• Experience with Metal stack optimizations.
• Experience performing Early Tech node analysis to identify implementation bottlenecks.
• Design Technology Co-optimization expertise.
• Strong analytical skills and ability to identify and communicate high return on investment opportunities.
• Ability to apply data science and ML analytics for Frontend and Backend databases, as well as post-silicon data, to identify trends & patterns and fine-tune implementation methodologies.