Digital Sign-Off Methodology Architect

Category Engineering Hire Type Employee Job ID 12690 Base Salary Range $171000-$256000 Remote Eligible Yes Date Posted 02/10/2025

You Are:

You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of Static Timing Analysis (STA), Power Analysis, Physical Verification, and EM/IR for advanced node designs. Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

• Develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries.
• Work with leading edge designs and teams to drive the industry best PPA for IP designs.
• Evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.
• Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
• Work as a liaison between EDAG tool and IP design teams.
• Continuously improve and refine design processes to enhance efficiency and performance.

• Drive innovation in high-speed digital IP core and Subsystem development.
• Enhance the efficiency and effectiveness of our design and verification processes.
• Contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems.
• Ensure the highest quality standards in the design and implementation of our products.
• Facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence.
• Support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

• BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.
• Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
• Direct hands-on experience with Primetime, Primepower/PTPX, Redhawk or industry equivalent tools.
• Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
• Good analysis, debugging, and problem-solving skills.
• Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
• Familiarity with other Synopsys tools such as StarRC, ICV, and experience with Ansys RedHawk is a plus.
• Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.