As part of Accenture's Industry X, the Silicon Design group is a diverse team of world-class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation, and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high-performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true "Silicon to SW" Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
Whether at our Silicon Design Center in Phoenix or at one of our other locations you will get to collaborate and innovate with the world's leading product development companies. In our dynamic fast-paced environment, you will get to make the impossible possible.
Accenture is invested in our team member's growth and provides many opportunities for training and skills expansion.
- Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, constraints , static timing analysis , formal verification, Gate level functional & timing ECO in advanced technology nodes
- Develop & document STA & Synthesis strateg ies. I nteract with methodology teams to address challenges related to new technology nodes.
- Familiar with constraint checking tools and techniques to deliver quality constraints for both pre and post CTS views.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
- Proficiency in advanced synthesis & STA techniques to achieve aggressive low power, area, and timing goals . Must be able to drive solutions for complex timing closure scenarios.
- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms
- Experience with multi-clock and multi-power domain designs.
- Proficiency with ECO for functional and DFT timing closure
- Deliver physical design of an end-to-end IP or integration of ASIC/SoC design
Here what you need:
- Bachelor's Degree or equivalent work experience (12 years) or an Associate's Degree with 6 years of work experience
- 7 years of experience in SoC Integration, Digital Design
- RTL2 Gate experience on advanced technology nodes (7nm andbelow)
- Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
- Experience in Block-level and Full-chip integration .
- Experience with Python, TCL, or Perl programming.
- Experience working with EDA tools like DC/Genus, ICC2/ Innovus , Primetime
- Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
- Knowledge of static timing analysis, defining timing constraints and exceptions, corners/voltage definitions
- Experience with Python, TCL or Perl programming
$83,200 - $168,499 and information on benefits offered is here.
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AZ - Phoenix,CA - San Jose