As part of Accenture's Industry X, the Silicon Design group is a diverse team of world-class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation, and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high-performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true "Silicon to SW" Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
Whether at our Silicon Design Center in Phoenix or at one of our other locations you will get to collaborate and innovate with the world's leading product development companies. In our dynamic fast-paced environment, you will get to make the impossible possible.
Accenture is invested in our team member's growth and provides many opportunities for training and skills expansion.
A Physcial Design Senior Staff Engineer:
- Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, static timing analysis, power analysis, IR Drop, EM, in advanced technology nodes
- Resolve power issues related to physical design, identify potential low power solutions, drive execution and methodology improvements
- Perform comprehensive power analysis in vector and vector-less modes of ASIC SoC design
Read more of the job description
Here's what you need:
- Bachelor's Degree or equivalent (12 years) work experience (If an, Associate's Degree with 6 years of work experience)
- Minimum of 3 - 10 years of experience in the following:
- RTL2GDSIIon advanced technology nodes (7nm and below)
- Low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF.
- Power constraints generation and validation, power analysis, interface with power integrity analysis tools.
- TCL, Python and/or Perl programming.
- EDA tools like DesignCompiler/Genus, Primetime/PrimePower, ICC2/Innovus, Redhawk/Voltus
Bonus points if,
- Experience running power analysis in vector and vector-less modes and achieving optimal QoR on low power designs
- Knowledge of static timing analysis, power analysis and concepts, defining timing and power constraints exceptions, switching activity definitions and simulation vectors
- Experience with power integrity analysis at block level or top level, including EM, IR & ESD analysis, power reduction techniques in SOC design
As required by theColorado Equal Pay Transparency Act, Accenture provides a reasonable range of minimum compensation for roles that may be hired in Colorado. Actual compensation is influenced by a wide array of factors including but not limited to skill set, level of experience, and specific office location. For the state of Colorado only , the range of starting pay for this role is $83,200 - $168,499 and information on benefits offered is here.
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AZ - Phoenix,CA - San Jose