Accenture Flex offers you the flexibility of local fixed duration project based work powered by Accenture, a leading global professional services company. Accenture is consistently recognized on FORTUNE s 100 Best Companies to Work For and DiversityInc's Top 50 Companies for Diversity lists.
As an Accenture Flex employee, you will apply your skills and experience to help drive business transformation for leading organizations and communities. In addition to delivering innovative solutions for Accenture s clients, you will work with a highly skilled, diverse network of people across Accenture businesses who are using the latest emerging technologies to address today s biggest business challenges. You will receive competitive rewards and access to benefits programs and world class learning resources. Accenture Flex employees work in their local metro area onsite at the project significantly reducing and or eliminating the demands to travel.
- Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floor-plan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
- Deliver physical design of an end-to-end IP or integration of ASIC/SoC design
- Bachelor's degree in Electrical Engineering or Computer Science
- 5 - 8 years experience
- RTL2GDSII experience on advanced technology nodes (7nm and below)
- Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF/CPF knowledge.
- Experience in Block-level and Full-chip floor-planning and power grid planning.
- Experience with Python, TCL, or Perl programming.
- Experience working with EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre
- Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
- Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions
- Experience in Block-level and Full-chip floor-planning, power grid planning
- Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques
- Experience with Python, TCL or Perl programming
$72,400- $114,499 and information on benefits is here
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AZ - Phoenix,CA - San Francisco