Senior Physical Design Engineer (RTL2GDSII)

City: Penang

State/Province: Penang

Posting Start Date: 2/12/26

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients' most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Job Description:

Job Description

Role Purpose
The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client

We are looking for Senior Physical Design Engineers with strong hands-on experience in RTL-to-GDSII implementation. The engineer should be capable of independently owning two or more design partitions of varying complexity.

The selected PEO will have end-to-end ownership of the Physical Design flow, starting from synthesis through PNR, Clock Tree Synthesis (CTS), timing closure, and physical signoff.

Key Expectations

• Own and deliver RTL2GDSII for multiple partitions
• Handle complete PD flow including:
• Synthesis
• Floorplanning, Placement, CTS
• Routing and optimization
• Timing closure across all corners
• Perform and close signoff checks, including:
• VCLP
• IR / RV
• FEV
• LVS / DRC
• Work independently with minimal supervision
• Drive issue resolution for timing, congestion, power, and physical verification
• Communicate effectively with internal teams and stakeholders

Skill Requirements

• Strong hands-on experience in:
• PNR
• Timing closure
• Physical signoff
• Proven ability to own blocks independently
• Good communication and coordination skills

Experience

• 5 years of relevant experience in ASIC Physical Design

• Senior Physical Design Engineer (RTL2GDSII)
• Looking for PD engineers with 5 years experience to independently own RTL-to-GDSII for multiple partitions.
• Strong hands-on expertise in PNR, CTS, timing closure, and physical signoff.
• Must have experience with VCLP, IR/RV, FEV, LVS/DRC.
• Good communication skills and ability to work independently.

Mandatory Skills: VLSI Physical Design Packaging .

Experience: 5-8 Years .

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.

Client-provided location(s): Nibong Tebal, Malaysia

Job ID: Wipro-136240

Employment Type: OTHER

Posted: 2026-02-14T18:45:22