Physical Design IPQA Engineer

City: Taipei

State/Province: Taiwan Prov.

Posting Start Date: 3/29/26

Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients' most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com.

Job Description:

Job Description

We are seeking a highly detail-oriented "Physical Design IPQA Engineer" to ensure the silicon-readiness and high-quality delivery of our IP portfolio. In this role, you will be responsible for the end-to-end Physical Design verification flow, utilizing CrossCheck and industry-standard EDA tools to validate GDSII, LEF, and Netlist consistency, with a specific focus on "TSMC advanced process nodes".

Key Responsibilities
• IPQA Execution： Perform comprehensive Physical Design checks, including Pin Label validation, GDS/CDL uniqueness, and GDS2RH view verification.
• Advanced Node Validation：Ensure all IP deliverables adhere strictly to "TSMC N3P and N2P" design rules and integration requirements.
• Cross-Tool Validation：Utilize CrossCheck tools to identify inconsistencies between timing models (lib), physical abstracts (LEF), and layout data (GDS).
• Physical Verification：Run and debug sign-off quality DRC (Design Rule Check) and LVS (Layout vs. Schematic) to ensure zero-defect IP delivery.
• EDA Tool Integration：Work within Synopsys (SNPS) and Cadence (CDNS) environments to perform LEF consistency checks and ensure compatibility across multiple PD flows.
• Quality Reporting：Document IPQA violations, coordinate with design teams for fixes, and provide final quality sign-off reports. Required Technical Skills |
• PD IPQA Expertise：Proven experience in IP Quality Assurance with a focus on the physical domain.
• Foundry Knowledge：Deep familiarity with "TSMC advanced nodes", specifically "N3P and N2P" process technologies.
• Design Collaterals：Extensive experience handling and validating "TSMC design collaterals", including PDKs, techfiles, and foundation IP kits.

• Tool Proficiency：Hands-on experience with CrossCheck and standard physical verification tools (e.g., Calibre, IC Validator, or Pegasus).
• Format Knowledge：Deep understanding of IP deliverables including GDSII, LEF, DEF, CDL, and .lib formats.
• EDA Ecosystem：Familiarity with Synopsys and Cadence Physical Design suites.
• Scripting：Ability to use Tcl, Python, or Perl to automate check runs and parse log files.

Preferred Qualifications
• Experience working with external EDA vendors for tool support and flow enhancement.
• Previous experience in a high-volume IP house or foundry environment.

Deliver
No. Performance Parameter Measure 1. Verification Timeliness
Quality of Code/ Number of defects
Customer responsiveness
Project documentation (scripts, test cases etc) 2. Self-development Skill test for next level clearance on Trend Nxt

Mandatory Skills: VLSI Physical Place and Route .

Experience: 3-5 Years .

Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention.