ASIC Engineer, Networking Architecture and Modeling

As a Networking ASIC Engineer on the Infrastructure Silicon team at Meta, you will play a key role in shaping the networking architecture for leading-edge AI training and inference accelerators. You will work closely with other architecture engineers to define networking architecture specifications and then develop high-fidelity C++ models-including QEMU, NIC, RoCE, and UAL (Ultra Accelerator Link) models-to enable early software development, architecture exploration, and performance analysis.You will collaborate with cross-functional teams working on data center networking architecture, network system design, micro-architecture, RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation, and Program Management to deliver first-pass functional silicon.

ASIC Engineer, Networking Architecture and Modeling Responsibilities:

• Collaborate with architecture engineers to define specifications for one or more subsystems of an integrated or discrete NIC ASIC
• Develop and maintain C++ models of networking subsystems-including QEMU, NIC, RoCE, and UAL models-for architecture exploration, performance analysis, and software development
• Provide technical support in functional model development to enable networking firmware creation
• Support networking model development, performance analysis, and correlation with design implementation
• Work with software and firmware teams to ensure C++ models are aligned with system requirements and enable early software bring-up
• Provide expected key performance indicators for performance analysis of the subsystems

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 6+ years of experience working in networking ASIC development targeted for enterprise, data-center, or hyperscaler use cases
• Hands-on experience developing and maintaining C++ models for NIC, RoCE, UAL or similar networking architectures
• Experience with QEMU or similar simulation frameworks for hardware modeling

• Experience working with large clusters of Ethernet or RoCEv2 or Infiniband or NVlink fabrics
• Knowledge of ASIC development on advanced process nodes using chiplet-based solutions
• Experience and knowledge of data center networking solutions used in large-scale clusters, including shallow buffered switches, TOR switches, routers, GPU and CPU servers/acceleration devices
• Experience in using performance models, performance analysis, and performance correlation
• Experience in developing PCIe-based NICs, Front-end and Back-end NICs
• Experience with QEMU NIC modeling, UAL modeling, and RoCE modeling using C++
• Experience integrating C++ models with system simulation environments (e.g., QEMU, SystemC, or custom frameworks)