AR Subsystem Power Architect

Reality Labs (RL) focuses on delivering Meta's vision through AI-first wearables devices. The compute performance and power efficiency requirements require custom silicon. The Reality Labs wearables team is driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable our wearables products to blend real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

AR Subsystem Power Architect Responsibilities:

• Develop and maintain architectural models and specifications for system-on-chip (SOC) components and subsystems
• Lead technical analysis and optimization efforts for SOC subsystem design elements, utilizing data from simulation and hardware validation platforms
• Conduct analysis and optimization of SOC subsystems to achieve optimal power, performance, and area (PPA) targets
• Drive architectural analysis for current and future workloads to inform SOC design decisions and roadmap planning
• Collaborate with cross-functional teams to deliver technical documentation, architectural specifications, and performance models for SOC implementations

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• 2+ years of experience integrating SoCs or complex IP-based subsystems as a Silicon Architect or Digital Design Engineer
• Knowledgeable in SoC system design principles and evaluating architectural trade-offs across key performance metrics including power, performance and area
• Experience with post-silicon to pre-silicon correlation analysis
• Experience with developing and utilizing telemetry solutions to analyze and profile workloads

• Demonstrated experience developing and maintaining power models for accelerator sub-systems
• Experience performing workload analysis for power across a range of relevant workloads, including next-generation applications
• Experience leading Intellectual Property (IP) power optimization analysis using traffic traces from pre/post silicon platforms
• Experience in at least one relevant area: Audio, Display, Rendering, Computer Vision, or Imaging
• Experience leading the analysis and configuration of subsystem caches for optimal PPA
• Experience with bare-metal programming, micro-benchmarking, etc
• Experience deconstructing a problem, designing performance experiments, analyzing and visualizing data, and drawing conclusions for modeling and subsystem architecture
• Experience collaborating with cross-functional partners to produce comprehensive documentation and modeling for workloads executed on accelerator sub-systems