Quality Engineering Lead

Infosys is a global leader in next-generation digital services and consulting. We enable clients in 56+ countries to navigate their digital transformation. With over four decades of experience in managing the systems and workings of global enterprises, we expertly steer our clients through their digital journey. We do it by enabling the enterprise with an AI-powered core that helps prioritize the execution of change. We also empower the business with agile digital at scale to deliver unprecedented levels of performance and customer delight. Our always-on learning agenda drives their continuous improvement through building and transferring digital skills, expertise, and ideas from our innovation ecosystem.

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Location- Taiwan

Responsibilities:
• First silicon debug with Design and OSAT Test Engineering.
• Defines test program flows and methods for solid test coverage.
• Drive final test yield analysis and corrective actions
• First silicon debug with Design and OSAT Test Engineering.
• Finalize wafer-sort and final test programs in support of production
• Drive product to meet yield and test time/cost goals.
• Analyze yield at Engineering Sample phase and Characterize NPI product performances and manufacturing yield window including bench correlation to meet product requirements.
• Identify and implement root cause solutions to yield loss mechanisms through statistical data analysis and failure analysis techniques.
• Transfer product knowledge to OSAT sustaining engineer
• Manage Test Contractor (OSAT) in early production stage

Basic Qualifications:
- Bachelor's degree in engineering, computer science or equivalent
- Knowledge of the semiconductor industry, processes, technologies and key suppliers
- More experience in semiconductor digital design, test and/or product engineering for complex SoC's
- Must have hands on experience & solid understanding of SOC development cycle in multiple ASIC projects
- Hands on experience in successful new product introductions for multiple complex, high-volume SoCs in advanced process nodes
- Strong knowledge of new product introduction from first silicon through product qualification and characterization
- Good analytical, communication, team work, and troubleshooting and problem solving skills required

Preferred Qualifications:
- Master's degree or Ph.D. degree in Electrical Engineering or related field
- Good knowledge and debugging skill on ATE (J750 & Advantest 93K is preferred)
- Chip design background in circuit/physical design (timing closure, power, etc.) or DV (correlating SW signatures to block level tests) is desirable
- Post silicon physical debug background in speed-path/Vmin, memory arrays, clocking, or yield improvements
- Post silicon logic debug background in exercising various DFX features, analyzing scan-dump/mem-dump, suggesting tests in both system level and in DV
- Product engineering background and familiarity with ATE coverage, margin, binning, scan pattern generation, etc
- Knowledge of CPU, DDR4/LPDDR4/LPDDR5, USB, eMMC, CSI/DSI & MIPI characterization is a highly desired

EEO Statement:

At Infosys, we recognize that everyone has individual requirements. If you are a person with disability, illness, or injury and require adjustments to the recruitment and selection process, please contact our Recruitment team for adjustment either via the following email Infosys_ta@infosys.com or call 1-866-472-0935. Alternatively, you can include your preferred method of communication in email, and someone will be in touch.