Sr. Principal Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems is looking for a highly motivated hardware engineer to work with the Modus R&D engineering team in the Design-For-Test (DFT) IP business unit.

As a member of the DFT R&D team, you will design and implement advanced Design-for-Test (DFT) hardware, test fabrics, and on-chip test networks used in next-generation SoCs. You will contribute to the hardware and software development of industry-leading test solutions such as scan compression, hierarchical test access architectures, Logic Built-In-Self-Test (LBIST), Memory Built-In-Self-Test (MBIST) , Power-On-Self-Test (POST), and In-System Test (IST). Your work will directly support high-coverage, low-cost test strategies across complex semiconductor designs.

Required Skills

• RTL Design & Verification
  • Strong background in Verilog/SystemVerilog RTL for digital hardware design and simulation
  • Hands-on coding and automation skills using SystemVerilog/Verilog, plus scripting with Perl and Python
  • Mastery of UVM and directed testbench IP verification, including test planning, coverage closure, debug, and working with verification teams to drive quality
  • Knowledge of network structures and method for communicating data across an SoC
• Full-Flow Development & Integration

• Proven experience developing complex reusable IPs from architecture through delivery
• Strong experience with synthesis, lint, CDC/RDC, formal checks, timing closure, physical design, and signoff workflows
• Ability to manage internal and third-party/services IP integrations, including requirements review, interface alignment, quality checks, and delivery tracking
• Ability to debug complex hardware issues across RTL, verification, synthesis, timing, and integration environments
• Strong documentation skills for architecture specs, design specs, integration guides, and verification collateral

• Experience with ISO 26262 functional safety concepts, including safety mechanisms, diagnostic coverage, safety requirements, and ASIL-oriented design flows
• Exposure to security-aware hardware design, including secure boot concepts, access control, lifecycle management, key handling, or secure debug
• Experience with automotive, industrial, AI, or hyperscaler-class IP development
• Familiarity with Cadence flows such as Xcelium, JasperGold, Genus, Innovus, Tempus, Modus, and related signoff/debug environments
• Experience driving IP maturity through reusable methodology, quality metrics, and scalable infrastructure