Sr Principal Program Manager

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Senior Principal Program Manager - Interface Controllers

Job Description Summary

We are looking for a Senior Technical Project Manager who will be responsible for the overall coordination of R&D Development Projects and Key Customer Engagements within the Design IP Group. The candidate must have solid, hands-on experience with PCIe, UCIe and/or Ethernet controllers and implementation in SoC with a history in successfully leading or managing designs with end customers. We are looking for an individual with an entrepreneurial mindset with strong leadership skills and "assume ownership" to ensure flawless execution. Someone who is passionate, and enjoys and thrives on coordinating all the facets of the design project in a matrix organizational structure to deliver successful results. Ability to manage multiple priorities, coordinate with R&D and marketing in defining the scope, and ability to collaborate with teams with clear communication skills, are the must-have attributes in this role.

Job Description

As a Program Manager you are responsible for driving the various internal teams to deliver Controller IP based products and services. You must be knowledgeable and proficient with Ethernet and PCIe standards, MAC and protocols. Additionally, proven experience to interpret the standard's specification to understand Interoperability and Compliance test suites. This position is responsible for creating and executing project plan, proactively mitigating risks, and managing the Project life cycle from inception to project delivery and post-production support. You will also be responsible for managing external stakeholders as customer facing Program Manager.

• Work with internal & external customers, stakeholders to define project objectives and requirements.
• Prioritize requirements and define scope to meet customer needs in a timely manner given available resources.
• Develop, maintain, and distribute (as appropriate) standard project management deliverables for the successful implementation of the project, including: implementation plan, project schedule, project budget and variances, issues & action items log, meeting minutes, risks assessment and contingencies.
• Manage deliverables (including SOWs, change management, approval of deliverables).
• Partner with internal and external development teams to deliver on time and with the quality required.
• Serve as the project owner in development process; maintaining quality checklists, Jira tickets, schedule tracker etc.
• Manage each release through the quality checker process.
• Partner with various teams to identify areas in need of improvement to increase customer satisfaction and decrease support requests.
• Anticipate problems and complications and formulate solutions so as not to impede the progress of the project.
• Assume responsibility and drive ownership for issue resolution.
• Holding status update meetings with technical teams and updating higher management on the project progress.
• Create and maintain scorecards to track project performance.
• Accountable for on time project delivery, product quality, cost, and operations.

• Bachelor's degree in engineering from an accredited institution.
• 15+ years of experience out of which at least 2+ years of Program Management or Technical Product Management experience in a technology-oriented organization.
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe
• Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards
• Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience to interpret the standard's specification reg. Protocol, Interoperability and Compliance test suites
• Strong project management skills with the ability to work on and track multiple projects simultaneously.
• Demonstrated ability to think creatively and strategically when executing the project and solving problems.
• Familiar with mixed-signal IP design flow and methodologies, Verilog/RTL coding & Verification