Sr Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a Sr Principal Verification Engineer to lead verification efforts for advanced IP development. This role involves architecting robust verification environments, driving methodology improvements, and mentoring team members. You will work closely with design and architecture teams to ensure first-pass success and high-quality deliverables.

Key Responsibilities

• Develop and maintain UVM-based verification environments for IP-level verification.
• Perform debugging of complex IP designs and resolve issues efficiently.
• Review and enhance verification test plans for completeness and coverage.
• Drive testbench development, simulation, and regression strategies.
• Mentor and guide junior engineers in verification best practices.
• Collaborate with cross-functional teams for seamless integration and delivery.

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.
• Minimum 10 years of experience in IP verification.
• Strong proficiency in SystemVerilog and UVM methodology.
• Expertise in debugging complex IP designs.
• Hands-on experience in testbench development and test plan reviews.
• Proven ability to mentor and lead verification teams.

• Experience in SERDES verification.
• Familiarity with UCIe protocol and chiplet integration.
• Knowledge of high-speed interfaces and related verification challenges.

• Work on cutting-edge IP technologies for next-generation SoCs.
• Opportunity to lead and influence verification strategy.
• Collaborative and innovative work environment.
• Competitive compensation and benefits.