Sr Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job responsibilities:

- Act as a tech consultant/leader, supporting/leading Cadence Digital Logic Verification platform related customer projects or pre-sales engagements in Vietnam further to whole AsiaPacific region.

- Work closely with the sales team to identify and scope opportunities for the Cadence solutions

- Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues

- Summarize the tasks and projects, and report to manager and share with team effectively

- Train, ramp-up and accompany customer project.

- Conduct basic and advanced trainings, presentations and demos as necessary.

- Ramp-up other members of the team on the advanced verification technologies and tools.

-Providing technical expertise to address clients' queries with answers/solutions

Requirements:

- Native Vietnamese speaker with good English writing and oral skills

- The candidate should possess CS or EE BS level with minimum10+ years, or MS level with minimum 8+ yrs of industry experience.

- Minimum 8+ years experiences in Digital Logic Design or Verification by EDA solutions.

- Candidate's years of experience will be mapped to different grades.

- Familiar with Digital Simulators (IES, Xcelium, VCS, Questa, etc) with strong simulation debugging skills.

- Deep hands-on experience on ASIC/SOC verification, general industry VIP usage or Verification IPs development.

- Familiar with Verilog/VHDL/SystemVerilog UVM is a must.