Sr Account Technical Executive II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Key Responsibilities

• Lead technical engagement for Digital IC/Custom IC / Analog / RF design flows, with a primary focus on Innovus and Virtuoso platforms along with signoff technologies
• Partner with customer design and CAD teams to optimize layout productivity, quality, and time-to-market
• Drive adoption of advanced capabilities such as:
  • Constraint-driven and automation-assisted layout
  • Device-level and full-chip layout methodologies
  • Advanced node layout challenges (FinFET, GAA)
  • EM and IR-aware layout and parasitic extraction flows
• Champion the integration of AI-driven design techniques, including:
  • Agentic AI workflows to automate design exploration, layout optimization, and verification tasks
  • AI-assisted decision-making for layout trade-offs including PPA, matching, and parasitics
• Translate customer pain points into actionable requirements for R&D and product engineering
• Provide technical leadership in methodology definition, flow development, and best practices
• Influence competitive replacements and expand footprint of Cadence Custom IC solutions
• Support executive-level discussions by linking technical value such as PPA, productivity, and risk reduction to business outcomes

• Deep hands-on experience with digital design flow including Genus/Innovus , Quantus , Tempus and Pegasus
  • Clear understanding of PPA tradeoff's and other key concerns for design teams
  • Ability to think full stack/flow - interconnect technologies and drive value proposition
  • Experience working with design teams on large SOC tapeouts
  • Understanding of foundry working model and care bouts - knowledge of PDK enablement , DTCO and technology entitlement a plus

• Deep hands-on experience with the Cadence Virtuoso Platform, including:
  • Virtuoso Layout Suite (XL, GXL, EXL)
  • Schematic-driven layout and LVS flows
  • DRC and physical verification integration
• Strong knowledge of custom analog and mixed-signal layout techniques, including:
  • Device matching, symmetry, common centroid, and shielding
  • Parasitic-aware layout for high-performance analog and RF circuits
• Experience with the Spectre simulation environment and layout-to-schematic integration
• Familiarity with PCell development, layout automation, and scripting (SKILL preferred)

• Strong understanding of AI and machine learning applications in semiconductor design, specifically:
  • Agentic AI frameworks such as multi-agent systems, goal-driven automation, and autonomous optimization
  • AI-assisted layout generation and design space exploration
  • Intelligent automation of repetitive design and verification tasks
• Experience or demonstrated interest in:

• Applying AI to EDA workflows, CAD flows, or design methodology optimization
• Working with data-driven or reinforcement learning-based optimization approaches

• 5-10 or more years of experience in:
  • Custom IC, Analog, or RF design or layout engineering
  • Mixed-signal design flows at block and full-chip level
• Deep understanding of:
  • Analog and RF design flows from schematic to signoff
  • Physical verification, extraction, and post-layout simulation
  • Advanced-node layout challenges and reliability considerations
• Experience with layout productivity optimization and methodology deployment at scale

• Proven ability to:
  • Engage deeply with CAD teams, design leads, and senior technical leadership
  • Identify and articulate technical gaps and business impact
  • Drive alignment between customer roadmap and Cadence product direction
• Strong communication skills with the ability to translate between deep technical detail and executive-level value

• BSEE required, MSEE or higher strongly preferred
• 5-10 or more years of experience in Digital IC , Custom IC, Analog, or RF design or layout
• Demonstrated expertise in Innovus-based and Virtuoso-based design environments
• Exposure to or strong interest in AI-driven design methodologies and agent-based automation frameworks
• Exposure to chiplet design flows , packaging and IP design a plus
• Strong collaboration and customer-facing experience
• Ability to travel approximately 25 percent, primarily within North America