Signal and Power Intgrity Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• We are looking for an experienced SIPI (System-In-Package Integration) Engineer to lead 3D-IC integration projects for complex HPC/AI chips. You will be responsible for developing and implementing advanced packaging SIPI solutions for high-performance AI applications. This is a challenging and rewarding opportunity for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.

• Design Engineer 1

• Job Description
  • Develop and implement comprehensive PDN analysis methodologies for complex 3DIC packages, including CPU, GPU, and TPU structures.
  
  • Perform detailed power noise and signal integrity simulations using tools like Cadence Sigrity PowerSI, Ansys HFSS, or equivalent.
  
  • Identify and resolve power integrity issues, such as IR drop, ground bounce, and signal noise, to achieve sign-off criteria.
  
  • Analyze and optimize signal integrity for high-speed interfaces in 3DIC packages, including HBM3, UCIE, and DDR5.
  
  • Perform advanced SI simulations using industry-standard tools like Cadence Clarity, HyperLynx, Ansys HFSS, or equivalent.
  
  • Extract parasitic from 3D package layout and integrate them into SI and PI simulations.
  
  • Develop and implement design rules and guidelines for 3DIC package and silicon SI and PI.
  
  • Collaborate with design engineers, layout engineers, and thermal engineers to optimize the PDN design and ensure proper heat dissipation.
  
  • Stay up-to-date on emerging 3DIC technologies and trends and propose innovative solutions to improve power integrity performance.
  
  • Document analysis results and findings clearly and concisely for internal and external stakeholders.
  
  • Participate in technical discussions and provide expert guidance on signal/power integrity matters.
• Additional Job Description
  • Bachelor's degree in electrical engineering, Computer Engineering, or a related field
  
  • 2 years of experience in SIPI or related field, In-depth knowledge of PDN design principles, including modeling, simulation, and optimization techniques.
  
  • Expertise in advanced SI simulation tools like Cadence Sigrity, Clarity, HyperLynx, HFSS, or equivalent.
  
  • Proven experience in leading and managing complex engineering projects
  
  • In-depth knowledge of 3D-IC packaging technologies, including chip stacking, interposers, and through-silicon vias (TSVs)
  
  • Proven experience with high-speed interface design and analysis (HBM, DDR, PCIe, etc.).
  
  • Strong understanding of thermal, signal integrity, and power integrity concepts
  
  • Excellent written and verbal communication skills.
  
  • Ability to work effectively in a team environment.

The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Client-provided location(s): San Jose, CA

Job ID: Cadence-R53094

Employment Type: FULL_TIME

Posted: 2026-02-06T18:41:12