Senior Principal Software Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our R&D team building next-gen Accelerated Verification IP (AVIP) and Virtual Bridge solutions for high-performance IO and memory coherence. You'll architect, implement, and productize PCIe Gen7 and CXL 2.0/3.x features across C++, UVM and virtualized system models that enable hardware, emulation, and hybrid platforms.

What you'll do

• Design and enhance PCIe/CXL AVIP (agents, monitors, scoreboards, sequencers, coverage, error injection).
• Develop Virtual Bridge components that connect virtual platforms/emulators/FW to RTL (traffic modeling, performance, debug).
• Own feature bring-up for CXL.io / CXL.cache / CXL.mem, IDE/security, RAS, switching/fabric (CXL 3.x).
• Deliver compliance and interoperability scenarios; drive customer escalations and cross-team integration.

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Experience with PCIe and/or CXL design/verification, deep protocol-layer knowledge (LTSSM, DLL/TLP, flow control, ordering).
• Proficiency in Verilog RTL design and debug
• Experience with emulation/acceleration or hybrid (virtual + RTL) flows; solid debug skills (waveforms, checkers, coverage).

• PCIe Gen6/CXL 3.x fabric features (multi-level switching, global fabric attach, pooling).
• Performance modeling, QoS/traffic shaping; firmware/OS driver bring-up exposure; compliance tools.