Senior Principal Design Engineer- Memory IP

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

Key Responsibilities:

• - Take ownership of the architecture and micro-architecture design for high-performance memory interface IPs, including DDR, LPDDR, and GDDR.

This involves developing and implementing RTL code for digital logic, managing RTL integration, and synthesizing and optimizing designs to improve timing and PPA (Power, Performance, and Area).

• - Collaborate closely with the Analog design team to understand their requirements and ensure alignment throughout the design process.
• - Partner with the verification team to analyze coverage reports, perform debugging as needed, and confirm that the design meets all specifications.
• - Interface with the Physical Design team to support Static Timing Analysis, timing closure, and Place & Route activities, ensuring seamless integration across disciplines.
• - Work with the validation team to provide support during silicon bring-up, helping to resolve issues and validate functionality.

Position Requirements:

• - Demonstrated proficiency in logic design and micro-architecture, with hands-on experience using Verilog/SystemVerilog and simulation environments.
• - Strong understanding of integrated circuit (IC) design principles, especially those related to high speed and low power.
• - Minimum of three years' experience working on digital IC development projects, with proven ability to lead and contribute effectively within a collaborative team environment.
• - Excellent communication skills, both verbal and written, are essential for success in this role.
• - BS degree with at least 5 years of relevant experience or MS degree with at least 3 years of applicable experience in electrical engineering, microelectronics, engineering science, or solid state physics.
• - Ability to communicate clearly in English is required.
• - Familiarity with JEDEC-DDR and DFI protocols and prior memory IP design experience are advantageous, though not strictly required.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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Client-provided location(s): San Jose, CA

Job ID: Cadence-R52252

Employment Type: FULL_TIME

Posted: 2026-02-24T18:39:43