Product Engineering Architect (3D IC, Heterogeneous Integration & Advanced Packaging)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Product Engineering Architect

Location: San Jose, California, United States

Reports to: Product Engineering Director

Job Overview:

As Product Engineering Architect, you provide senior technical leadership for the development and proliferation of Cadence Virtuoso Heterogeneous Integration technologies. In this role, you partner closely with strategic customers, Product Management, R&D, Product Validation, and Application Engineering teams to define product strategy, drive innovation, and ensure successful delivery of complex technical solutions.

As an architect, you combine deep technical expertise with market understanding to shape the product roadmap for the physical implementation flows around 3D IC, heterogeneous integration and advanced packaging. You will drive team-level technical objectives throughout the development cycle and lead early customer engagements.

Job Responsibilities:

• Drive, validate and promote an end-to-end solution for system design implementation flows spanning 3D IC, heterogeneous integration and advanced packaging.
• Lead strategic customer engagements, guiding customers to define and deploy advanced heterogeneous integration and multi-die co-design methodologies.
• Influence product roadmap direction by synthesizing customer requirements, market trends, competitive insights, and technical feasibility.
• Produce high-quality Product Requirement Specifications (PRS), technical use cases, and support R&D during product development.
• Provide technical leadership, including requirement trade-off analysis, solution validation, adoption risk assessment, and prioritization of critical bugs and enhancements.
• Mentor and guide product engineers and cross-functional team members on complex design-flow challenges, technical decision-making and customer communication.
• Create executive- and customer-ready technical collateral, demonstrations, application workflows, and enablement materials that accelerate field and customer adoption.
• Represent product engineering in roadmap discussions, customer reviews, product launches, and industry events.
• Collaborate cross-functionally with R&D, Product Management, Field teams, Technical Publications and Product Validation to deliver robust, customer-ready capabilities.
• Own deliverables from definition through customer deployment with a strong focus on execution and accountability.

• BS in Electrical Engineering, Electronics, or a related technical field.
• Deep expertise in semiconductor design, physical implementation, advanced packaging, or EDA product engineering.
• Strong hands-on knowledge of the Cadence Virtuoso platform and associated custom IC design flows, with the ability to connect detailed technical issues to broader product strategy.
• 15+ years of relevant experience in product engineering, methodology development, customer enablement, or technical leadership roles.
• Demonstrated ability to shape technical direction and align cross-functional stakeholders around high-value deliverables.
• Proven track record working with strategic customers, including discovery of complex requirements, executive-level technical communication, and successful deployment of advanced design flows.
• Ability to lead through influence, mentor technical contributors, prioritize effectively, and drive team-level technical objectives.
• Strong verbal and written communication skills, with the ability to collaborate effectively across global and multicultural teams, and across functions.
• Highly motivated by the rapidly evolving landscape of 3DIC, heterogeneous integration, and advanced packaging technologies, with a passion for driving innovation in next-generation semiconductor solutions.

• Experience with co-design flows around 3D IC, heterogeneous integration, and silicon-package-board integration.
• Knowledge of Cadence Allegro Package Designer Plus (APD+) and package implementation methodologies.
• Knowledge of Cadence Virtuoso SKILL language or any other interpreted language.