Principal Software Engineer - Low Power Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

About the Role

We are seeking a highly skilled Senior Software Engineer to join our team in developing next-generation low-power verification software for Palladium and Protium emulation systems. This role focuses on enhancing the debuggability and performance of multi-billion-gate UPF (Unified Power Format) designs in modular compilation 2-state and 4-state flows.

Key Responsibilities

• Develop and optimize low-power verification software for Palladium and Protium platforms.
• Improve UPF design debuggability in IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state flows).
• Enhance compiled streaming probes and accelerate waveform generation for large-scale designs.
• Collaborate with R&D, Product Engineering (PE), and Application Engineering (AE) teams to deploy UPF solutions across various flows:
  • AVIP + UPF + 2/4-state
  • UVMA + UPF + 2/4-state
  • MC + UPF
  • Dielets + UPF
• Consolidate UPF software across Palladium and Protium platforms.
• Support key initiatives such as:

• MC+PPC flow with UPF 4-state
• Compilation time optimization for UPF
• Full Vision UPF probe integration
• SAGE UPF debug with Verisium

• Bachelor's degree in Computer Science or Electrical Engineering with a minimum of 7 years of relevant experience,
  or Master's degree with 5+ years of experience,
  or PhD with 1+ year of experience.

• Strong proficiency in object-oriented design and C++ programming.
• Experience with standard C/C++ libraries and the C++ Standard Template Library (STL).
• Proven ability to develop high-performance software for large-scale data processing.
• Scripting experience in Perl, Tcl/Tk, and/or Python.
• Familiarity with IEEE 1801 standards and UPF implementation.
• Experience with Verilog, SystemVerilog, and VHDL.