Principal Product Engineer

▸ Mentor junior and senior product engineers, providing technical guidance and code/flow reviews on complex implementation challenges.
▸ Drive automation initiatives in Tcl, Perl, Python, and Shell to build scalable infrastructure for regression testing, benchmarking, and customer flow replication.
▸ Represent Cadence DSG in customer technical reviews, design-for-manufacturability (DFM) workshops, and industry conferences.
▸ Influence product roadmap decisions by synthesizing customer feedback, competitive landscape insights, and internal R&D capabilities into actionable recommendations.

What You Bring

▸ BE, MS in Electrical Engineering or related discipline
▸ 6-8 years of deep, hands-on experience in ASIC physical design and/or EDA product engineering, with a demonstrable track record of shipping designs or product improvements.
▸ Expert-level understanding of the full RTL-to-GDSII flow: synthesis, floor-planning, placement, CTS, routing, static timing analysis, and physical sign-off.

▸ Proven experience with timing closure and PPA optimization at 16nm and below - including 10nm, 7nm, and 5nm FinFET processes.
▸ Deep proficiency with Cadence Innovus Implementation System, Tempus Timing Signoff Solution, and Genus Synthesis Solution; familiarity with Pegasus Physical Verification is a strong asset.
▸ Advanced expertise in static timing analysis: multi-mode multi-corner (MMMC), POCV/AOCV, hold-time optimization, and clock domain crossing (CDC) methodology.
▸ Thorough understanding of hierarchical design methodologies - interface timing modeling (ITM/ETM), blackbox flows, and top-level integration.
▸ Extensive knowledge of low-power design: IEEE 1801 UPF, multi-voltage domains, power gating, retention strategies, and dynamic voltage/frequency scaling.
▸ Strong scripting and automation skills: Tcl (advanced), Perl, Python, and Shell; experience building reusable flow infrastructure is highly valued.
▸ Demonstrated leadership in technical problem-solving with an organized, data-driven approach and the ability to influence cross-functional teams.
▸ Excellent communication skills - able to present complex technical content clearly to executive stakeholders, customers, and R&D partners alike.

Leadership & Soft Skills

▸ Proven ability to lead cross-functional technical projects, from initial scoping through delivery and documentation.
▸ Experience in customer-facing roles with the gravitas to manage high-stakes technical discussions under pressure.
▸ Comfort operating independently in a fast-paced, matrix organization while driving accountability and results.
▸ Passion for staying at the forefront of semiconductor design trends, with an ability to translate emerging challenges into product opportunities.

Nice to Have

▸ Experience with Cadence Joules RTL Power Solution, Voltus IC Power Integrity, or Innovus-Tempus integrated signoff flows.
▸ Knowledge of advanced routing constraints: self-aligned double patterning (SADP), EUV-specific design rules, and advanced via optimization.
▸ Familiarity with chip design in automotive (ISO 26262), AI/ML accelerator, or HPC application domains.
▸ Prior experience in an R&D engineering role at an EDA or semiconductor company.

Why Cadence?

▸ Shape the future of EDA - your work directly influences tools used to design next-generation processors, SoCs, and AI chips.
▸ Collaborative, high-Caliber team of engineers working on the world's most complex implementation challenges.
▸ Competitive total compensation package including equity, performance bonuses, and comprehensive benefits.
▸ Strong focus on continuous learning, with access to industry conferences, internal training, and research partnerships.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

Client-provided location(s): San Jose, CA

Job ID: Cadence-R54972

Employment Type: FULL_TIME

Posted: 2026-06-03T18:43:03