Principal Application Engineer - Verification

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a highly skilled Senior SoC Verification Engineer with 6+ years of hands-on experience in complex SoC verification. The ideal candidate has strong expertise in UVM-based environments, deep understanding of SoC architecture, and practical experience verifying application processors, AI accelerators, or other high-performance chips. This role focuses on technical depth rather than people management, requiring strong ownership, problem-solving ability, and broad protocol knowledge.

Key Responsibilities

• Develop and execute verification plans for complex SoC subsystems and full-chip environments.
• Build, enhance, and maintain UVM-based verification environments, including agents, sequences, scoreboards, and coverage models.
• Perform block-level, subsystem-level, and SoC-level verification, including IT (Integration Test), UT (Unit Test), and ST (System Test).
• Verify integration of third-party IPs, custom logic, and system-level features.
• Debug functional issues across RTL, testbench, and SoC integration layers.
• Analyze coverage metrics, identify gaps, and drive closure for functional, code, and assertion coverage.
• Collaborate closely with design, architecture, and validation teams to ensure design intent and testability.
• Support bring-up and validation on emulation/FPGA platforms when required.
• Contribute to continuous improvement of verification methodologies, automation, and infrastructure.
• Document test plans, test results, and verification reports with clarity and completeness.

• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of hands-on experience in digital SoC verification.
• Strong proficiency in SystemVerilog, UVM, constrained-random verification, and coverage-driven methodology.
• Solid understanding of SoC architecture, memory hierarchy, cache systems, interconnects, and coherency concepts.
• Experience verifying AP (Application Processor), AI accelerator, DSP, multimedia, or high-performance compute SoCs is highly desirable.
• Broad familiarity with industry-standard protocols such as AXI, AHB, APB, PCIe, USB, DDR, LPDDR, MIPI, Ethernet, or similar.
• Strong debugging skills using waveform tools, assertions, and simulation logs.
• Hands-on experience with simulation, emulation, or acceleration platforms.
• Knowledge of low-power verification (UPF), formal verification, or performance validation is a plus.
• Ability to work effectively in cross-functional and multi-site teams.
• Strong communication skills and ability to articulate technical issues clearly.
• Self-driven, detail-oriented, and comfortable working in fast-paced environments.

• Experience with AI/ML hardware verification or high-bandwidth compute subsystems.
• Familiarity with Python, Perl, or shell scripting for automation.
• Exposure to post-silicon validation flows.
• Understanding of DFT concepts and scan/MBIST interactions.