Lead Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Overview:

We are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment.

Job Responsibilities:

• Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
• Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
• Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
• Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
• Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.
• Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.

• Bachelor's degree in electrical engineering, computer engineering with 4 years of work experience or master's degree in electrical engineering, computer engineering with 2 years of work experience.
• Proven expertise and hands-on experience in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
• Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
• Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
• Strong programming skills in Verilog, System Verilog and Python
• Excellent communication skills and the ability to thrive in a team-oriented environment.
• Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.

• Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.