Lead Application Engineer

In this role, you will develop customer specific emulation and prototyping requirements, including advanced acceleration component development, methodology support, and operation and maintenance of Cadence's emulation and prototyping tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Palladium acceleration and emulation platform and Protium prototyping platform. You will create and conduct technical presentations and product demonstrations for customers.

Key Responsibilities:

Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support
Provide in-depth technical assistance in collaboration with R&D to help support advanced verification flows to secure design wins
Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions
Understand the competitive landscape and continuously work on differentiating Cadence's solutions
Write technical product literature such as application notes and technical articles
Review new product proposals and device specifications
Assume technical leadership roles in small teams as needed

Requirements:

Minimum
BS, MS.or PhD degree in Computer Science, Engineering, or related field
Strong RTL and Testbench debug skills
Experience in synthesizable coding style
Experience in writing scripts (Perl, Python or TCL)
Strong software, HDL design and verification skills
Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC
Ability to quickly analyze verification environments and design complexity
Strong verbal and written communication skills
Strong teamwork skills
Ability to interact effectively with both external customers and R&D teams
4+ years industry experience

Preferred
Experience in HW acceleration, in-circuit emulation or FPGA prototyping
Experience with multiple clock domains and asynchronous interfaces
Knowledge of the FPGA development process & tool flow from RTL to bitstream for Xilinx and/or Altera products
Hands on experience with lab bring up, debug, chipscope and instrument usage
Experience with C/C++/SystemC
Knowledge of fundamental SoC Architecture knowledge
Understanding of wmbedded software development and HW/SW co-design and co-verification
Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR
Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing

The annual salary range for California is $102,900 to $191,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

Client-provided location(s): San Jose, CA

Job ID: Cadence-R52104

Employment Type: FULL_TIME

Posted: 2025-12-04T18:42:19