Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

职位名称: 数字前端设计工程师

工作地点: 南京

工作职责:

• 参与高速数字电路及相关 IP 子系统的架构设计、模块设计与功能验证
• 负责或协助完成 ASIC 中数字模块的 RTL 设计、仿真及调试工作
• 配合后端、验证及系统团队，支持项目在各阶段的顺利推进

任职要求:

• 微电子、电子工程、计算机工程或相关专业硕士学历
• 有高速接口、复杂数字系统IP 设计项目经验者优先
• 具备扎实的数字电路基础，理解 ASIC 设计和验证的完整流程
• 熟悉硬件描述语言Verilog/VHDL，熟悉Perl/Tcl/C shell/Python/Makefile等脚本语言
• 具备良好的中英文沟通与技术文档写作能力，善于分析问题，具备较强的学习能力和团队合作精神

Position Title: Design Engineer - Frontend Design
Location: Nanjing, China

Responsibilities:

• Participate in the design and verification of high-speed digital circuits and related IP subsystems
• Contribute to RTL design, simulation, and debugging of digital modules in ASIC projects
• Collaborate closely with verification, backend, and system teams to ensure smooth project execution across different stages

Requirements:

• Master in Microelectronics, Electrical Engineering, Computer Engineering, or related fields
• Experience with high-speed interfaces, complex digital systems, or IP design/verification projects is a plus
• Solid foundation in digital circuit design with a clear understanding of ASIC design and verification flows
• Proficient in hardware description languages such as Verilog and/or VHDL, Experience with scripting languages such as Perl, Tcl, C Shell, Python, and/or Makefile
• Strong written and verbal communication skills in both Chinese and English; good problem-solving abilities and strong teamwork mindset

We're doing work that matters. Help us solve what others can't.

Client-provided location(s): Nanjing, China

Job ID: Cadence-R52553

Employment Type: FULL_TIME

Posted: 2026-01-09T18:38:15