Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Design Engineer II

Location: Cork, Ireland

Reports to: Design Engineering Director

Job Overview:

AI infrastructure is driving demand for Ethernet at speeds that didn't exist five years ago.

The Ethernet IP team in Cadence Cork is building the controller IP (MAC, PCS, FEC) at the heart of that infrastructure, operating at speeds up to 1.6 Terabits per second under IEEE 802.3dj.

The full design team is based in Cork, covering RTL design through to silicon delivery under one roof - creating a highly collaborative environment where engineers can see their work progress end-to-end.

We're looking for an engineer early in their career to contribute to RTL blocks within our high-speed Ethernet controller IP.

You'll work alongside a senior team that not only implements the latest IEEE 802.3 and Ultra Ethernet Consortium (UEC) specifications but also contributes to shaping them.

• Contribute to the RTL design of blocks within high-speed Ethernet MAC, PCS, and FEC IP cores (10G through 1.6T), from micro-architecture through coding, lint, and CDC sign-off
• Work with the latest IEEE 802.3dj and Ultra Ethernet Consortium (UEC) specifications, contributing to architecture discussions on multi-rate, multi-port controller designs
• Collaborate closely with verification engineers on test plan reviews, coverage, and bring-up of new features
• Partner with back-end teams on synthesis, timing closure, and area/power trade-offs for configurable IP delivery
• Participate in design and code reviews, contributing to continuous improvement in design quality across the team

• Bachelor's or Master's degree in Electronic/Electrical Engineering, Computer Engineering, or a related discipline
• Experience in digital design through one or more of the following:
  • Approximately 2+ years of industry experience in RTL design (ASIC or FPGA), or
  • A research-based Master's degree (MEng / MSc) in a relevant area such as digital design, networking, communications, or signal processing, or
• Equivalent hands-on experience demonstrating strong RTL design capability
• Working knowledge of Verilog or SystemVerilog, and core digital design fundamentals (e.g. RTL design, FSMs, clocking, CDC, timing)
• Analytical and problem-solving skills, with the ability to take a design from specification through to implementation with support from the wider team
• Good communication skills and ability to collaborate effectively across design, verification, and back-end teams

• Experience with simulation and debug tools (e.g. Xcelium, VCS, ModelSim, or similar)
• Exposure to Ethernet standards or high-speed networking
• Awareness of Forward Error Correction (FEC) or signal integrity concepts

• Competitive salary
• 25 days holiday per year
• Private Medical and Dental plans, Income Protection and Life Insurance
• Group Personal Pension Plan
• Cycle to work scheme and gym subsidy
• 5 days paid time to volunteer to give back to our communities
• Employee Stock Purchase Plan
• The opportunity to work for a Great Place to Work© & Fortune 100 organization