Application Engineer II: Physical Design - Synthesis and Digital Implementation

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineer II: Physical Design - Synthesis and Digital Implementation to work with us in Belo Horizonte, Brazil.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

As an Application Engineer, you will be part of Global Customer Success (GCS) - ASK team in Belo Horizonte, Brazil. The ASK team works with Digital, Analog, Verification, Systems tools and provides application support to all Cadence customers. To understand more on our tools & flows, you can visit https://www.cadence.com

Job Description:

• Support customers in improving productivity and design quality using Cadence digital implementation flows, with emphasis on logic synthesis and physical design.
• Assist in debugging design, flow, and tool-related issues,
• Learn and apply best practices for timing, area, and power optimization in synthesis and implementation.
• Collaborate with R&D, senior AEs, and field teams to reproduce issues, validate solutions, and improve tool usability.
• Develop technical documentation, examples, and enablement material to promote self-service and tool adoption.
• Contribute to custom solutions using tool features and basic scripting to address customer challenges.

• Complete Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related fields.
• Solid foundation in CMOS fundamentals, digital logic, and RTL design concepts.
• Exposure to digital design flows (e.g., RTL → synthesis → implementation).
• Basic experience with scripting languages such as TCL, Python, or Perl.
• Strong analytical, debugging, and problem-solving skills.
• Ability to learn complex technical topics and clearly communicate findings.

• Academic or internship exposure to logic synthesis and/or physical design concepts.
• Familiarity with static timing analysis (STA) fundamentals.
• Basic understanding of standard cell libraries and process technologies.
• Prior exposure to Cadence digital tools (Genus, Innovus) or other EDA tools.
• Experience with Linux-based development environments.

• Employment category: CLT.
• Employment term: 40 hours/week
• This position is based in Belo Horizonte, Brazil.
• Competitive benefits.