Application Engineer I: Digital Verification & Simulation

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineer I: Digital Verification & Simulation to work with us in Belo Horizonte, Brazil.

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

As an Application Engineer, you will be part of Global Customer Success (GCS) - ASK team in Belo Horizonte, Brazil. The ASK team works with Digital, Analog, Verification, Systems tools and provides application support to all Cadence customers. To understand more on our tools & flows, you can visit https://www.cadence.com

Job Description:

• Assist customers in improving verification productivity and simulation performance using Cadence digital verification tools and flows.
• Support debug of functional and simulation-related issues, including waveform analysis, testbench behavior, and tool usage.
• Learn and apply best practices for RTL simulation, regression flows, and coverage analysis.
• Collaborate with senior Application Engineers, R&D, and field teams to reproduce issues, analyze root causes, and validate solutions.
• Develop technical documentation, examples, knowledge articles, and enablement material to improve customer self-service.
• Contribute to custom verification solutions using tool capabilities and basic scripting techniques.

Minimum Requirements:

• Complete Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related fields.
• Solid foundation in digital logic, RTL design, and simulation concepts.
• Understanding of hardware description languages such as SystemVerilog or Verilog.
• Familiarity with simulation-based verification concepts (testbench, stimulus, checking).
• Basic experience with scripting languages such as TCL, Python, or Perl.
• Strong analytical, debugging, and problem-solving skills.
• Ability to learn complex technical topics and communicate technical findings clearly.

Nice to Have:

• Academic or internship exposure to functional verification flows.
• Basic understanding of SystemVerilog testbench concepts (interfaces, assertions, randomization).
• Familiarity with coverage concepts (code coverage, functional coverage).
• Prior exposure to Cadence verification tools, especially Xcelium, or other simulators.
• Experience with Linux-based development environments.

Additional Job Details:

• Employment category: CLT.
• Employment term: 40 hours/week
• This position is based in Belo Horizonte, Brazil.
• Competitive benefits.

About Cadence Design Systems:

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.

We're doing work that matters. Help us solve what others can't.

Client-provided location(s): Belo Horizonte, Brazil

Job ID: Cadence-R54394

Employment Type: FULL_TIME

Posted: 2026-04-18T18:55:02