Application Engineer I: Digital Simulation/Verification & Agentic AI

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineer I: Digital Simulation/Verification & Agentic AI to work with us in Belo Horizonte, Brazil.

As an Application Engineer, you will support customers and internal teams in digital verification and simulation flows using Cadence Simulation and Verification tools. You will be part of System & Verification Group (TFO-SVG) in the Systems Verification Simulation group. This role focuses on learning and applying Agentic AI to make verification tasks smarter and more efficient. You will work closely with senior engineers to automate processes, improve coverage, and help customers adopt innovative AI-driven solutions.

Working at Cadence is very dynamic, fast-paced, and integrated with other teams all around the world, at this opportunity you will work with cutting-edge Agentic AI in real-world simulation/verification flows and hands-on experience with industry-leading tools like Cadence Xcelium™, Verisium.

Job Description:

• As an Application Engineer you will be responsible to provide technical support, helping Cadence customers to effectively deploy our industry leading Verification products and Assist with Simulation Flows, helping set up and run simulations using Xcelium.
• Learn and Apply Agentic AI: Use AI tools to simplify repetitive tasks and improve verification speed.
• Systems Automation: Write simple scripts (Python or TCL) to automate routine steps.
• Support Verification Tasks: Work with UVM-based environments and learn coverage analysis.
• Collaborate with Teams: Join technical discussions and training sessions to grow your skills.

• Complete Bachelor's degree in Computer Engineering, Electrical Engineering, or a related field.
• Knowledge of SystemVerilog and digital design concepts.
• Interest in AI technologies and their application in engineering workflows.
• Familiarity with scripting languages (Python, TCL).
• Good communication skills and willingness to learn.
• Understanding of RTL design and coding (Verilog, VHDL)
• Excellent written and verbal communication skills in English and Portuguese.
• Strong analytical and problem-solving skills.

• Experience with Unix and C/C++
• Knowledge of design fundamentals such as architecture, micro-architecture, HDL synthesis, and timing
• Verification skills including UVM testbench architecture, development and debugging, System Verilog, and SVA
• Understanding of SoC architecture fundamentals
• Familiarity with embedded software development and HW/SW co-design and co-verification
• Proficiency in scripting languages (Perl, Python, TCL, Bash, etc.)

• Employment category: CLT
• Employment term: 40 hours/week.
• Competitive benefits.
• Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.