Wireless RTL Design Engineer

Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.

Description

In this role, you will develop high-performance low power ASIC design for wireless MAC. you will be at the center of a silicon design group, with a critical impact on getting innovative and functional products to hundreds of millions of customers quickly.","responsibilities":"Writing specifications and other document

Microarchitecture definition

RTL logic design, IP integration, and verification support

Running front-end tools to ensure lint-free and CDC/RDC clean design

Synthesis and timing constraints

Power analysis and optimization

Collaboration with system and software team to ensure functionality, performance, and power efficiency

Develop and maintain methodology/ flow/ checks for your design

Preferred Qualifications

Hands on experience in ASIC design flow

Proven track record of high performance designs in high volume production for low power applications

Hands on experience in computer architecture including one or more of the following: Bus fabric, especially APB/AHB/AXI, Memory systems, System debug architecture, Power management with multiple power domains, Encryption/decryption engines, Integer and floating-point numeric units, High-speed data path and control units.

Experience in ASIC design front end flows - Lint, CDC, STA, LEC

Knowledge and experience in MAC layer of wired/wireless communication system preferred

Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee preferred

SoC top-level integration experience and system architecture knowledge is a plus

Proficiency in HDL languages, such as Verilog / SystemVerilog

Proficiency in scripting languages (Shell, Perl, Python)

Ability to work well in a team and be productive under aggressive schedule

Excellent communication skills and self-motivation/organization

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience

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