STA Engineer
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Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.
Description
As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis.
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Preferred Qualifications
Strong fundamentals in the area of Digital design
Familiarity with ASIC design timing concepts
Proficient in scripting languages (TCL, Python and Perl)
Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus
Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks
Self-starter and highly motivated
Ability to communicate optimally across all internal groups
Minimum Qualifications
Bachelors Degree + 0 Years of Experience.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Perks and Benefits
Health and Wellness
Parental Benefits
Work Flexibility
Office Life and Perks
Vacation and Time Off
Financial and Retirement
Professional Development
Diversity and Inclusion
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