Senior FPGA Engineer
At Apple, we strive every single day to craft products that enrich people's lives. Our successes are the result of skilled domain experts working in an environment which encourages creativity, collaboration, and re-thinking of old problems in new ways! As a member of the Satellite Connectivity Group, you will work on the satellite network that enables connectivity to iPhone and Watch Ultra when off the grid without cellular or Wi-Fi coverage. Every day, Apple customers use Emergency SOS, Roadside assistance, and Messages via satellite to stay connected when they have no other means to communicate. You will have the unique and rewarding opportunity to shape this and other critical services, to the benefit and safety of millions of Apple device users.
Our team is looking for an experienced FPGA / SoC engineer with System Verilog, High-level Synthesis (HLS/C++), and Python skills and experienced in software-defined-radio and/or real-time data-processing systems.
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Description
A successful candidate will be responsible for designing, implementing, testing, and operating a complex real-time software system that runs on a globally-distributed heterogeneous compute platform and processes every bit of information exchanged to realize the satellite connectivity. ","responsibilities":"Design, development, test of FPGA IPs in System Verilog and HLS for a software-defined-radio system built on AMD/Xilinx SoC.
Cross-team coordination and execution of software releases and hardware-software integrated test and production operation campaigns.
Preferred Qualifications
General radio-frequency (RF) digital signal processing knowledge.
Hands-on development experience in areas related to 5G, WiFi, GNSS, CCSDS, and/or SpaceWire.
Minimum Qualifications
10+ years of experience of designing and implementing high-bandwidth data-processing application on Xilinx FPGA / SoC platforms in System Verilog or HLS.
5+ years of experience of designing FPGA accelerators in HLS (Xilinx Vitis HLS).
5+ years of experience of workflow automation, data analysis, and data visualization in Python.
Ability to design the CPU-FPGA interface based on the standard protocols (AXI-MM, AXI-Stream) and the standard Linux subsystems (contiguous memory allocation, user I/O, device tree).
Ability to set up a Yocto Linux or Petalinux project for a custom Xilinx SoC board from scratch.
Ability to write kernel-space user-space device drivers in C++ for high-bandwidth and real-time hardware accelerators / custom peripherals.
Knowledge of and ability to mentor other team members on modern design/coding best practices.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Perks and Benefits
Health and Wellness
Parental Benefits
Work Flexibility
Office Life and Perks
Vacation and Time Off
Financial and Retirement
Professional Development
Diversity and Inclusion
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