RTL Design Engineer
Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.
Description
In this role you will work on a small team dedicated to IP architecture, design, and verification. As a member of the team you will be asked to architect and design new modules while working with multiple cross-functional teams including: Design Integration, Platform Architecture, Software Engineering, DFT, and Debug. You will write formal verification to prove the designs (when feasible). All designs will be written in SystemVerilog and will use SV simulations and SVA formal verification environments. You will run quality checkers (lint, CDC, RDC) and be expected to provide constraints and waivers when necessary. You will be asked to support the DV simulation team and the bring-up teams with the usage of new IP modules. All new designs are required to have documentation, example code (where relevant), and integration notes. Expect to give presentations to cross-functional teams on the new IP designs.","responsibilities":"Architecting and documenting new modules
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Coding designs in SystemVerilog
Running FV & DV at module level
Checking your design with industry standard static tools such as LINT, CDC, RDC
Analyzing and optimizing area, timing, and power
Preferred Qualifications
Fluency in SystemVerilog Assertions
Background in low power design
Understanding of embedded software design
Experience in diagramming architectures and presenting designs to integration/software teams
Minimum Qualifications
BS and a minimum of 3 years relevant industry experience
Fluency in RTL design using SystemVerilog
Experience designing for one or more AMBA protocols - AHB, AXI, APB
Working knowledge of synthesis and static timing analysis
Comfortable with clock domain crossings as well as CDC/RDC checking tools
Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .
Perks and Benefits
Health and Wellness
Parental Benefits
Work Flexibility
Office Life and Perks
Vacation and Time Off
Financial and Retirement
Professional Development
Diversity and Inclusion
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