RFIC - PLL Design Engineer

Would you like to join Apple's growing wireless silicon development team? The wireless RFIC team architects, designs, and validates radio transceivers integrated into complex wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. As Sr. RFIC - PLL Design Engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group with a critical impact on getting Apple's state-of-the-art wireless connectivity solutions into hundreds of millions of products.

Description

As a RFIC-PLL Designer, you are going to contribute to providing analog and digital PLL solutions for wireless SoC and driving them to mass production for Apple's Wireless Connectivity products.","responsibilities":"Design and develop analog and digital PLL building blocks: VCO, DCO, MMD, PFD, Filter, TDC and so on.

Design and develop analog and digital PLL top levels.

Design and develop LOGEN building blocks and top level.

Work with cross-functional teams including platform architecture, wireless design, RF HW and SW to define radio features enabling wireless innovation.

Work closely with RF Systems in block level and top-level specifications of the PLL, LOGEN, as well as TX and RX line ups, and proper distribution of spec margins in the chain.

Contribute to feasibility studies and trade-off analysis

Contribute to design starting from concept, architecture and topology to actual transistor-level design and verification

Work through Co-Existence scenarios and design to meet requirements.

Oversee layout, floor planning and verification of the design toward a successful tape-out.

Collaborate closely with RFIC test engineers in the bring up, debug and optimization of the chip throughout the productization.

Provide design versus silicon measurements correlation, and compliance with specification for a volume production.

Preferred Qualifications

Ph.D. degree

Hands on experience in modeling, analysis and design of noise/spur cancellation techniques in PLLs.

Familiarity with various RF transceiver architectures and their trade-offs, system specifications and ability to work with system architects to translate system requirements into circuit requirements at IC level.

Familiarity with timing analysis tools (Nanotime, Primetime).

Direct experience in designing and bringing into mass production of wireless transceivers in deep sub-micron RFCMOS technology.

Demonstrated capability to work with digital design group for an optimum partition between digital and analog and contribute to providing comprehensive timing requirements.

Minimum Qualifications

BS and 10 + years of relevant industry experience.

Experienced in design and development of Analog and Digital PLLs and LOGEN for high performance applications.

Hands on experience in designing PLL building blocks: TDC, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCO/VCOs and PFD/CP.

Deep understanding of analog, mixed-signal and RF circuit design concepts. This includes LNAs, PAs, mixers, baseband filters, VGAs and calibration methods associated with high performance wireless systems.

Experienced in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and similar tools.

Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS).

Extensive experience in PLL and LOGEN silicon characterization and debug.

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