Physical Design Engineer

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Description

APPLE INC has the following available in Austin, Texas. Collaborate with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs; Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle; Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals; Time, physical and electrical verification, and driving the signoff closure for the partitions; Resolve and improving design and flow issues related to physical design, identifying potential solutions, and driving execution; Work with logic designer to decide on design hierarchy and to architect macro/design module placement to extract best PPA at floorplan stage; Work with EDA tools to optimize the design to get best placement location for millions of cells in the design; Construct clock tree to support high performance and low power designs; Route the design to meet all latest technology foundry guidelines and rules; Verify design performance using Static analysis, generating ECOs to fix failing paths; Verify design for electrical rules checks, designing rule checks, electromigration and IR drop. Fix any of the violations on physical database; Review and signoff the design to make sure quality and PPA is not compromised; Identifying issue, debugging, resolving flow issues during place and route implementation; Develop scripts/programs as needed to implement and signoff designs; Understand weekly handoff requirements and run flows to delivered required data; and Work with IP leads to understand design violations and deliver fixes. 40 hours/week.

Preferred Qualifications

N/A

Minimum Qualifications

Bachelor's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering or a related field.

Experience and/or education must include:

Utilizing experience using industry standard tools for PnR to implement and signoff off SOC design partitions.

Utilizing industry stand timing tools to perform STA across multiple corners and modes, fixing setup and hold violations and debugging timing paths to ensure design meets timing and frequency specifications.

Creating a block-level floorplan including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction.

Utilizing skills to run and debug DRC and LVS using tools to complete PV signoff and ensure design meets foundry DRM specs.

Generating and analyzing clock trees, reducing skew and jitter, and optimizing buffer insertion to ensure CTS and performance specs are met.

Performing manual and tool-driven ECOs for timing (buffer insertion, cell sizing) for final STA signoff and closure of design.

Utilizing skills in power (leakage recovery, Vt swaps) and functional changes (gate-level patching) to ensure design is meeting power specifications

Utilizing skills in TCL and Shell Scripting to automate PnR flows, parse reports, or create CAD utilities.