DRAM Packaging Engineer
Join the team at the heart of memory innovation for every Apple product. As a DRAM Packaging Engineer, you will architect the memory solutions that power the industry-leading performance of Apple's hardware. We push the boundaries of computation, power efficiency, and system integration through meticulous co-design between memory technology and our world-class SoCs. If you are driven to solve the industry's toughest packaging challenges, your work will have a profound and lasting impact on the products used by millions.
Description
• In this role, you will drive the definition, development, and qualification of next-generation memory packages critical to Apple's future products.
• You will act as the central technical lead, guiding the roadmaps of our memory partners and collaborating with internal SoC and System teams to ensure flawless integration.
• Your ownership will span the entire product lifecycle, from initial architectural concept through qualification.","responsibilities":"Determine the technical direction of next generation memory subsystems by analyzing package technologies and quantifying DRAM die and SoC trade-offs with silicon architects.
Collaborate with cross-functional teams-including SoC Packaging, Design, SI/PI, and Thermal-to define memory component for optimized, system-level solutions.
Solve complex electrical and mechanical integration challenges of memory packages incorporated into advanced packaging technologies such as CoWoS, EMIB, SoIC, and PoP.
Define and document the memory package specifications, including architecture, layout, and bill of materials.
Drive package failure analysis during qualification to ensure world-class quality and reliability.
Partner with memory vendors, internal and industry stakeholders to develop roadmap for high-stack and 2.5D/3D memory package components.
Preferred Qualifications
MS and or Ph.D. with 10+ years of industry experience focused on HBM and high-performance memory.
Deep expertise with HBM architecture: TSV design, die stacking (CoW/WoW), memory organization, pseudo-channels, and thermal management.
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Strong knowledge of package and silicon co-design principles for high-throughput interfaces (e.g., UCIe, D2D, HBM)
Deep understanding of advanced memory packaging for DDR, LPDDR, HBM, and 3D integration thermal and mechanical challenges.
Demonstrated ability to solve complex engineering tradeoffs using data-driven analysis.
Excellent communication skills for collaborating with internal teams and managing external vendors.
Minimum Qualifications
BS and 10 +years of relevant industry experience.
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