Design Verification Engineer
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Description
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Build block/chip level testbenches using best-in-class verification methodologies. Create detailed verification plans from specifications in coordination with architects. Develop reusable block/IP level test benches and support IP integration verification. Generate directed and constrained random tests. Create and analyze coverage models and enhance testbenches/tests to increase coverage. Build automated flows for block and chip level verification. Debug failures, manage bug tracking, and close coverage. Hold detailed verification reviews and set standards for coding quality. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $216,091 - $272,100/yr and your base pay will depend on your skills, qualifications, experience, and location.
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PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Preferred Qualifications
N/A
Minimum Qualifications
Master's degree or foreign equivalent in Electrical Engineering, Electrical and Computer Engineering or related field and 5 years of experience in the job offered or related occupation.
5 years experience in the following skills are required:
Utilizing experience in Hardware Verification Language (HVL) and Hardware Design Language (HVL) including System Verilog or Verilog for Verification Environment and test development.
Utilizing experience with IP verification method and integration verification.
Utilizing knowledge of HVL methodology (UVM, OVM, or VMM) for constrained random test development.
Applying verification skills in problem solving, constrained random testing, and debugging.
Understanding of reusable verification framework to help speedup verification process.
Utilizing knowledge of digital logic design, chip architecture and microarchitecture to help analyze and debug RTL design.
Apply Industry standard protocol knowledge in developing monitor/checker and analyzing RTL design.
System Verilog Assertion (SVA) for verification.
Using Python/Perl scripts to develop verification test bench as well as post process verification results.
Defining coverage space and writing coverage model to measure verification quality and find verification holes.","internalDetails":null
Perks and Benefits
Health and Wellness
Parental Benefits
Work Flexibility
Office Life and Perks
Vacation and Time Off
Financial and Retirement
Professional Development
Diversity and Inclusion
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