Design Verification Engineer

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Description

APPLE INC has the following available in Austin, Texas. Verify RTL designs on an ASIC chip. Create System Verilog test benches within the UVM framework. Craft test plans and debug tests. Craft embedded C code tests. Review design and architecture specifications for next generation SOCs and IPs, and work closely with design and micro-architecture teams to understand the functional & performance goals of the design. Develop test plans, coverage plans, and define methodology and test benches. Implement block/full chip environments and test cases. Run regressions, perform bug tracking, analyze code and functional coverage. Ensure deliverables align with the project goals and support cross-functional engineering teams. 40 hours/week.

Preferred Qualifications

N/A

Minimum Qualifications

Bachelor's degree or foreign equivalent in Computer Engineering or a related field.

Experience and/or education must include:

Utilizing Verilog and SystemVerilog to work on ASIC verification

Utilizing UVM and OOP concepts to make code reusable

Utilizing Python and Perl to write automation scripts and speed up constructing test benches

Utilizing C and C++ to perform full-chip level chip verification

Utilizing skills associated with I2C, SPI, and UART to verify peripherals

Utilizing UNIX skills to locate and manipulate files and directories in the Terminal application

Utilizing skills associated with computer architecture to understand hardware RTL

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