Design Verification Engineer
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Description
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure bug-free first silicon for part of the SoC / IP and develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Learn to develop verification plans for all features, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features, and debug of the test failures. Develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. Work on pre-silicon ser-des(Serializer De-serializer )PHY verification of complex IO protocols like PCIe, Usb4. Develop verification environment for manufacturing screening DFT patterns. Develop post silicon sequences from verification environment for re-use for silicon validation. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 - $272,100/yr and your base pay will depend on your skills, qualifications, experience, and location.
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PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Preferred Qualifications
N/A
Minimum Qualifications
Bachelor's degree or foreign equivalent in Electronic Engineering, Electrical Engineering, or a related field and 5 years of progressive, post-baccalaureate experience in the job offered or related occupation.
3 years of experience with each of the following skills is required:
Performing Constraint Random Verification using Universal Verification Methodology (UVM)
Developing Verification Ips using System Verilog and Universal Verification Methodology (UVM)
Implementing System Verilog and System Verilog Assertions coding
Scripting using TCL/Perl or Python
Microcontroller/CPU based SOC/IP verification
Implementing and verifying pre-silicon design to prototyping platforms like Emulation
Debugging pre silicon failures with industry standard tools like Verdi or Indago
DFT verification with JTAG/1500 standards in pre-silicon environment to ensure Silicon can be debugged or brought up error free.","internalDetails":null
Perks and Benefits
Health and Wellness
Parental Benefits
Work Flexibility
Office Life and Perks
Vacation and Time Off
Financial and Retirement
Professional Development
Diversity and Inclusion
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