Design Verification Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Ensure the quality of the SOC or an IP or subsystem. Review design and architecture specifications and work closely with design & microarchitecture teams. Understand the functional & performance goals of the design and use knowledge to test effectively. Develop test plans, tests & coverage plans as well as define our next generation verification methodology & test benches. Communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases; and run and triage regressions, track bugs, and analyze coverage to achieve top results. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $194,700/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Preferred Qualifications

N/A

Minimum Qualifications

Master's degree or foreign equivalent in Electrical and Computer Engineering, Electronics Engineering or related field.

Experience and/or education must include:

Utilizing System Verilog to build scalable and reusable testbenches for SoC verification

Scripting using Perl and Python for testbench simulation flows automation

Using digital design concepts for functional verification of RTL DUT (design-under-test)

Utilizing Computer Architecture concepts for verifying SoC architecture and design

Utilizing System Verilog to create constrained random stimulus for RTL DUT verification (design-under-test)

Utilizing UVM to build test benches for constrained random verification of SoC IPs

Utilizing design verification concepts such as functional coverage metrics for SoC design verification