Design Verification

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Description

APPLE INC has the following available in Austin, Texas. Work closely with architecture and RTL designers on verifying the functionality correctness of the design. Develop test plans and test environments, Develop tests in assembly, C, or vectors according to test plans. Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered. Develop checkers or C-base transactor to verify the design. Develop synthesizable test bench components to enable high throughput emulation based validation. Debug and enhance simulation and emulation based collateral to enhance model throughput via DPI optimizations and other approaches. Assist in performance collateral optimizations. 40 hours/week.

Preferred Qualifications

N/A

Minimum Qualifications

Master's degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include:

Experience in computer architecture to understand design and debug functional failures.

Utilizing verilog or system verilog to create test bench components.

Utilizing C or C++ to create transactors for verifying the design.

Experience in digital logic to understand design and debug functional failures

Experience in verification of digital systems to generate tests and coverage monitors.

Experience in parallel computer architecture to verify multi-core computer systems.

Experience in VLSI to understand design and debug functional failures.

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