Custom Timing and Verification CAD Engineer

Apple's custom silicon is among the most sophisticated in the world - and getting it right requires rigorous transistor-level timing verification and formal verification at every step. Our Custom Timing CAD team builds and owns the flows, tools, and methodologies that make that verification possible. We are looking for an entry-level engineer who is eager to learn, technically curious, and excited to work at the intersection of circuit design and CAD engineering.

Description

In this role, you will support and develop flows for two of the most critical sign-off disciplines in custom IC design - transistor-level timing verification using NanoTime and formal verification using ESP. You will partner closely with analog and digital designers across multiple programs and technology nodes, helping them set up flows, debug issues, and achieve clean sign-off. The work you do will directly shape the quality and schedule of Apple's most advanced chips.

Responsibilities:

Develop, maintain, and improve CAD flows and automation scripts for NanoTime and ESP

Support design teams in setting up timing and verification runs, interpreting results, and resolving tool and methodology issues

Drive timing and formal verification closure in collaboration with circuit designers

Contribute to methodology documentation and guidelines adopted across programs and design organizations

Engage with EDA vendors to report issues, evaluate new features, and drive tool improvements

Build automation to improve flow efficiency, reduce runtime, and scale support across concurrent programs

Preferred Qualifications

Hands-on experience with transistor-level timing and formal verification tools such as NanoTime, ESP, PrimeTime, or HSPICE, including flow ownership and methodology development

In-depth knowledge of dynamic logic, memory arrays, or mixed-signal circuit techniques, and ability to debug complex timing and verification issues independently

Experience with SPICE netlists, device models, and parasitic extraction formats such as DSPF or SPF in the context of timing sign-off

Experience with formal verification methodologies and SystemVerilog RTL, including RTL-to-schematic equivalence checking

Track record of driving cross-functional collaboration with design, layout, and EDA vendor teams to resolve tool and methodology issues

Experience developing or contributing to organization-wide CAD methodology documentation and best practices

Familiarity with AI/ML-driven CAD workflows and interest in applying GenAI techniques to flow automation and timing analysis