CPU Processor Power Management Verification Engineer

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In this highly visible role, you will be at the center of a chip design effort collaborating with many teams, with a critical impact on getting functional products to millions of customers quickly. We are looking for a strong candidate to join our processor verification team focusing on Power Management and Clock Control verification.

Description

As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows:

• Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic

• Develop and execute test plans and schedules for the power management and clock control logic

• Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments

• Root cause failures and propose potential solution to the design team

• Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design

• Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered

• Develop checkers or Verilog/System Verilog-base transactor to verify the design

• Write assertions and apply formal verification to the design

Preferred Qualifications

Master's degree preferred

Knowledge of digital logic, micro-processor architecture and power management architecture

Proficiency in programming and scripting in Python, or Perl, or TCL

Experience or academic knowledge in design verification methodology. Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers

Knowledge of system Verilog assertions or other advance verification techniques such as formal verification is a plus

Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification efforts

Be able to follow detailed work schedules and work independently on the verification efforts for a block/area of the design

Minimum Qualifications

Minimum BS

Academic experience in computer architecture

Academic experience in digital design using Verilog

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .