Skip to main contentA logo with &quat;the muse&quat; in dark blue text.

CAD Engineer, Silicon Learning and Static Timing Analysis

3 days ago Santa Clara, CA

Do you love tackling highly complex challenges with a keen eye towards revealing what has been hidden to others? Do you intrinsically understand the difference between correlation and causation? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC) working on leading edge semiconductor technology nodes where the hidden details make a real difference in performance, power, and area. Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices and things that they haven't yet imagined possible.

In this critical role, you will be responsible for analyzing silicon performance data and incorporating the learnings back into static timing analysis tools, flows, margins, and design closure methodologies to drive continuous improvements in Apple products. You will help refine our understanding of advanced silicon to truly optimize performance and battery life in phones, laptops, and products not yet dreamt of.

Want more jobs like this?

Get jobs in Santa Clara, CA delivered to your inbox every week.

Job alert subscription


Description

Work with design teams, DFT, CAD, and product engineering to design experiments, analyze results and refine design methodologies applied across all silicon design at Apple.

Drive adoption of new technologies in the field of static timing analysis

Data mining and analysis of silicon data to establish correlation metrics to design closure activities including Static Timing Analysis

Develop and deploy design closure margins and methodologies targeted to optimize power/performance tradeoffs which have material impact on the final products

Preferred Qualifications

Experience working in static timing analysis, DFT, physical design, failure analysis or CAD

Static Timing Analysis with Primetime, Tempus, or equivalent

Solid C, Perl, Python or Tcl coding/debug skills coupled with an understanding of the design challenges in advanced technology nodes

Fundamentals of statistics, hypothesis testing, data mining, Machine Learning and Design of Experiments.

Prior exposure to DFT, Tetramax, Tessent, silicon debug, or semiconductor processing is a plus.

Minimum Qualifications

Minimum requirement of BS + 20 years of relevant industry experience

Coding experience in one or more of C, Perl, Python, or Tcl

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Client-provided location(s): Santa Clara, CA
Job ID: apple-200632127-3760_rxr-658
Employment Type: OTHER
Posted: 2025-11-17T19:08:46

Perks and Benefits

  • Health and Wellness

    • Parental Benefits

      • Work Flexibility

        • Office Life and Perks

          • Vacation and Time Off

            • Financial and Retirement

              • Professional Development

                • Diversity and Inclusion

                  Company Videos

                  Hear directly from employees about what it is like to work at Apple.