Principal SerDes Systems Engineer - 18231

What You'll Be Doing:
* Lead end-to-end SIPI for high-speed interfaces including PCI Express (Gen6/7/8), E224G, E448G, CXL (over PCIe), and other SerDes interfaces, spanning on-die, interposer, package, PCB, connectors, and compliance fixtures.
* Drive channel modeling and correlation across time- and frequency-domain analysis: S-parameters, TDR, crosstalk, ICN/ ccICN , ERL/ dERL , jitter/noise budgeting, equalization tradeoffs (TX/RX FFE/DFE/CTLE ),eye margin simulation, and link margining.
* Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI model extraction/model quality checks, de-embedding, and ensuring models are bandwidth-appropriate for target data rates.
* Partner with circuit/PHY, interposer/package, board, and product teams to diagnose bring-up and lab issues; propose design fixes and quantify risk/benefit via simulation and measurement.
* Plan and run correlation experiments (bench characterization, compliance testing support, fixture design guidance) and document learnings as reusable design guidelines.
* Define, improve, and document SIPI flows, requirements, and checklists for internal teams and (where applicable) customers; mentor engineers and lead technical reviews.
* Provide technical leadership across programs: set priorities, identify cross-project reuse opportunities, and influence architecture choice s impacting signal integrity and power integrity.

The Impact You Will Have:
* Enable first-pass success of high-speed SerDes IP and system integrations by defining robust SIPI signoff criteria and delivering validated, correlated methodologies.
* Reduce schedule risk by rapidly diagnosing complex cross-domain issues (silicon/package/board/lab) and guiding practical design changes backed by quantitative analysis.
* Raise the technical bar by mentoring others, standardizing best practices, and influencing architectural decisions for next-generation interconnects.
* Improve product performance and reliability by ensuring thorough modeling, simulation, and correlation to hardware in diverse environments.
* Drive innovation in SIPI methodologies, enabling scalable, reusable flows across multiple programs and product lines.
* Foster a culture of collaboration and continuous improvement within the team and across partnering organizations.

What You'll Need:
* B.S. (M.S./Ph.D. preferred) in Electrical/ Electronic Engineering or related field.
* 1 2 + years of relevant experience in high-speed SI/PI for SerDes links (silicon + package + board), preferably in interface IP or high-volume product development.
* Strong fundamentals in EM, transmission lines, passive/active modeling, and statistical link analysis; comfortable translating system requirements into measurable/signoff criteria.
* Expertise with high-speed link concepts: insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization, BER, etc.
* Deep expertise with modeling, simulation and EM tools (HSPICE, Keysight ADS/ Syste m Vue , Ansys HFSS/ SIwave /AEDT, Cadence Sigrity , Mathworks SIMULINK) and model formats (Touchstone, IBIS-AMI, SPICE, EM-based RLGC).
* Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter measurements, de-embedding/fixture calibration) and working alongside validation/compliance teams.
* Proficiency in scripting/automation for flow enablement (Python preferred; MATLAB/TCL is a plus) and a disciplined approach to documentation and reproducibility.
* Demonstrated technical leadership: mentoring, design reviews, influencing cross-functional decisions, and communicating complex topics clearly to mixed audiences.

Who You Are:
* Analytical and detail-oriented, with a passion for tackling complex engineering challenges.
* Collaborative and communicative, able to work effectively across multi-disciplinary teams.
* Proactive and resourceful, constantly seeking opportunities to optimize processes and drive innovation.
* Mentor and leader, committed to sharing knowledge and empowering others.
* Disciplined and organized, with a strong focus on documentation, reproducibility, and best practices.
* Adaptable, able to thrive in fast-paced, dynamic environments.

The Team You'll Be a Part Of:

You will join a global SerDes/PHY design team , a nd will int eract wit h package and board engineering, validation, and product teams to deliver high-performance interface IP. The team values rigorous analysis, strong correlation to hardware, and practical engineering judgment. Together, we drive innovation and enable our customers to achieve first-pass success in advanced system environments.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

Client-provided location(s): Boxborough, MA

Job ID: ansys-18231

Employment Type: OTHER

Posted: 2026-08-08T18:52:45