Power Integrity Senior/Staff Engineer

Date posted 07/09/2026
Category Engineering Hire Type Employee Job ID 18114 Remote Eligible No Date Posted 07/09/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of power delivery, where a poorly placed decap or a miscalculated target impedance can tank an entire PHY bring-up. The difference between a clean power rail and one that introduces jitter into a multi-gigabit link is something you see in your sleep, and you know how to catch it before tape-out. You think in frequency domains and transient responses, not buzzwords.

• Lead end-to-end power integrity analysis across die, package, and PCB for UCIe PHY and high-speed I/O systems, from VRM to on-die power grid
• Develop and optimize Power Delivery Network architecture, performing DC IR drop, AC impedance, transient response, and resonant analysis
• Build and validate electrical models for silicon, package substrates, PCBs, decoupling capacitors, and voltage regulators using S-parameters, IBIS, and SPICE
• Define target impedance requirements and analyze simultaneous switching noise, ground bounce, and power-induced jitter
• Collaborate with package, PCB, signal integrity, and PHY teams to optimize decoupling strategies and power distribution topologies
• Support silicon bring-up by correlating lab measurements with simulation results and refining models for future designs

• Enable next-generation UCIe PHY performance by delivering clean, reliable power to multi-gigabit interfaces in chiplet-based systems
• Define power integrity methodology and sign-off criteria that will be reused across future high-speed I/O platforms at Synopsys
• Reduce design respins and time-to-market by catching power delivery issues early through rigorous simulation
• Drive the success of AI and HPC accelerator products by ensuring power integrity in advanced 2.5D and 3D IC packaging technologies
• Improve PI analysis efficiency across the team by developing automation scripts and reusable simulation frameworks
• Shape design guidelines for die-package-board co-design that will influence Synopsys IP roadmaps

• Master's or Ph.D. in Electrical Engineering with 5+ years of hands-on experience in Power Integrity or high-speed interface design
• Deep understanding of Power Delivery Network design, including DC IR drop, AC impedance, transient analysis, and resonance mitigation
• Proven experience with die-package-board co-design for high-speed interfaces such as UCIe, PCIe, DDR, SerDes, or HBM
• Proficiency with PI tools such as Cadence Sigrity, Ansys SIwave, Ansys HFSS, Ansys RedHawk-SC, Keysight ADS, or PowerSI
• Strong working knowledge of S-parameters, IBIS/IBIS-AMI modeling, SPICE simulation, and frequency-domain analysis
• Scripting experience in Python, Tcl, or MATLAB for automation and data analysis

• You can translate between PHY designers and package engineers without losing technical accuracy
• When a simulation result does not match your intuition, you dig into the model assumptions rather than accepting the number
• You approach problems methodically but know when to pivot quickly, especially when a design decision is blocking downstream work
• You stay organized across multiple concurrent analyses, keeping track of which simulations are running and which results need communication
• You correlate lab data with simulation not to prove you were right, but to make the next model better