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25 jobs
Sr ASIC Design Verification Engineer (NetSec)
At Palo Alto Networks - Santa Clara, CA
Posted on Jun 19
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Posted on May 21
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Posted on May 21
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Posted on May 21
Sr. ASIC Design Verification Engineer (Silicon Engineering)
Posted on May 21
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Posted on May 29
Sr. ASIC DFT Engineer (Silicon)
Posted on May 29
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Posted on May 26
Sr. ASIC DFT Engineer (Silicon)
Posted on May 29
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Posted on May 26
Sr. RTL Design Engineer (Silicon Engineering)
Posted on May 21
Sr. ASIC DFT Engineer (Silicon)
Posted on May 29
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Posted on May 26
Sr. RTL Design Engineer (Silicon Engineering)
Posted on May 21
Sr. RTL Design Engineer (Silicon Engineering)
Posted on May 21
Sr. Full Chip Physical Verification Engineer (Silicon Engineering)
Posted on May 1